aosp-riscv
openc910
| aosp-riscv | openc910 | |
|---|---|---|
| 7 | 42 | |
| 348 | 1,047 | |
| - | 2.0% | |
| 4.3 | 1.3 | |
| over 2 years ago | 5 months ago | |
| C | Verilog | |
| Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
aosp-riscv
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Dual core Xuantie 910 out of order RISC-V SBC available for preorder
The boards are different but the chip has the same markings as in this board running AOSP on RISC-V.
https://github.com/T-head-Semi/aosp-riscv
So it should have a 3rd RV64GC + Vector draft 0.7.1 core.
- Dual core Xuantie 910 out of order RISC-V SBC available for preorder.
- Android 10 ported to RISC-V
- Android 10 on RISC-V architecture
- Android 10 AOSP ported to XuanTie C910 RISC-V
- AOSP (Android 10) port to RISC-V
openc910
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US Government reportedly ponders crimping China's use of RISC-V
> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.
The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.
> All Chinese RISC-V core designs have been proprietary designs thus far.
There is the OpenC910 [1] and OpenXiangShan [2].
[1] https://github.com/T-head-Semi/openc910
- Lichee Console 4A – RISC-V mini laptop: Review, benchmarks and early issues
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
Note that the C910 CPU cores used in this chip are in fact open source:
https://github.com/T-head-Semi/openc910
(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
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This CPU is FREE!
The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910
- LTT
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China Deploys RISC-V Server in Commercial Cloud
More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.
https://github.com/T-head-Semi/openc910
The SG2042 is the most powerful RISC-V SoC available today.
In which direction is the technology transfer going?
[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August
[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer
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Raspberry Pi receives strategic investment from Arm
For "coming down the pipeline" they're essentially free.
Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.
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Lichee Pi 4A: Serious RISC-V Desktop Computing [video]
Here is the source code* for the CPU:
https://github.com/T-head-Semi/openc910
* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.
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Beagleboard BeagleV-Ahead RISC-V brd released
The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.
https://github.com/T-head-Semi/openc910
The same cores are used in the 64 core SG2042 workstation/server SoC.
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ARM’s Cortex A53: Tiny but Important
It's a shame, because it was the best design from ARM; they're now focusing on Cortex-A7x and Cortex-X, which aren't anywhere as power efficient[0].
Meanwhile, their revised Cortex-A57 has been surpassed in performance/power/area by several RISC-V microarchitectures, such as SiFive's U74[1], used in the VisionFive2 and Star64, or even the open source XuanTie C910[2][3].
0. https://www.youtube.com/watch?v=s0ukXDnWlTY
1. https://www.sifive.com/cores/u74
2. https://xrvm.com/cpu-details?id=4056743610438262784
3. https://github.com/T-head-Semi/openc910
What are some alternatives?
openc906 - OpenXuantie - OpenC906 Core
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
XiangShan - Open-source high-performance RISC-V processor
seL4 - The seL4 microkernel
awesome-riscv - 😎 A curated list of awesome RISC-V implementations
riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
vroom - VRoom! RISC-V CPU
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
clash - A rule-based tunnel in Go.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU