openc910 VS rsd

Not noted here is that the fastest RISC-V general purpose machines you can currently buy use the THead C910 core, which is:

1) Chinese

2) actually Open Source (except the vector unit): https://github.com/T-head-Semi/openc910

The fastest off the shelf RISC-V machine currently is the Milk-V Pioneer using the SG2042 SoC which has 64 C910 OoO cores running at 2.0 GHz, with 64 MB L3 cache and up to 128 GB RAM. The core, SoC, board, and PC are all made in China.

Of course this situation changes very fast. There will be several machines using SiFive's P550 cores in several months -- most from Chinese companies, or at least using Chinese SoC (SiFive's own HiFive Premier P550 board). And then at the end of the year the Milk-V "Oasis" (and others from at least Sipeed) using SiFive's P670 cores, but again in the Chinese SG2380 SoC.

There are a several US startups who started work on RISC-V core in 2021-2022 who will have much faster (Apple M1 class or better) cores, but those won't arrive in machines you can buy until 2025 or 2026.

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.

The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.

> All Chinese RISC-V core designs have been proprietary designs thus far.

There is the OpenC910 [1] and OpenXiangShan [2].

[1] https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source:

https://github.com/T-head-Semi/openc910

(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.

https://github.com/T-head-Semi/openc910

The SG2042 is the most powerful RISC-V SoC available today.

In which direction is the technology transfer going?

[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August

[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free.

Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here is the source code* for the CPU:

https://github.com/T-head-Semi/openc910

* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

Some cores are open source and you can see for yourself.

Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:

https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...

From RSD, a core designed for FPGAs written in SystemVerilog:

https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...

And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?

https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...

So I had a look at the repo cause it sounded interesting and it turns out I understand the comments even less than the code. :|

Linux support is planned.

BOOM is RV64GC targeting silicon. BOOM supports the full privileged ISA and can run OSes like Linux; it's not clear if RSD supports the privileged architecture. Skimming their CSRFile code it looks like it only implements a thin machine mode?