aosp-riscv
openc906
| aosp-riscv | openc906 | |
|---|---|---|
| 7 | 14 | |
| 348 | 318 | |
| - | 2.2% | |
| 4.3 | 3.4 | |
| almost 3 years ago | 4 months ago | |
| C | Verilog | |
| Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
aosp-riscv
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Dual core Xuantie 910 out of order RISC-V SBC available for preorder
The boards are different but the chip has the same markings as in this board running AOSP on RISC-V.
https://github.com/T-head-Semi/aosp-riscv
So it should have a 3rd RV64GC + Vector draft 0.7.1 core.
- Dual core Xuantie 910 out of order RISC-V SBC available for preorder.
- Android 10 ported to RISC-V
- Android 10 on RISC-V architecture
- Android 10 AOSP ported to XuanTie C910 RISC-V
- AOSP (Android 10) port to RISC-V
openc906
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Milk-V Duo: A $9 RISC-V COMPUTER
Datasheet: https://github.com/milkv-duo/hardware
Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906
The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.
They list H.264/H.265 support, but I don't think it's a standardized extension.
But see my other comment about using the pre ratification vector extension:
- New RISC-V SoCs. Are they private and secure, or just more of the same?
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ARM versus RISC-V
Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.
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Core2Duo doesnt have backdoor
Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!
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Google wants RISC-V to be a “tier-1” Android architecture
Try and see if you can find any stolen code here[0] or here[1].
Cheers.
0. https://github.com/T-head-Semi/openc906
1. https://github.com/T-head-Semi/openc910
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RISC-V Pushes into the Mainstream
I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.
- Store access fault when executing AMO instructions in Nezha D1
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Does a truly secure Linux system exist?
For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.
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Buying RISC-V development board
For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906
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Packed-SIMD (P) vs Vector (V) extension
For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.
What are some alternatives?
openc910 - OpenXuantie - OpenC910 Core
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
riscv-profiles - RISC-V Architecture Profiles
riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU
linux - Patches include sunxi platform support and various driver fixes
vroom - VRoom! RISC-V CPU
duo-files
XiangShan - Open-source high-performance RISC-V processor
riscv-isa-sim - Spike, a RISC-V ISA Simulator
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cvitek-linux-5.10