XiangShan
ibex
XiangShan | ibex | |
---|---|---|
32 | 21 | |
4,318 | 1,250 | |
1.2% | 1.9% | |
9.9 | 8.3 | |
5 days ago | 1 day ago | |
Scala | SystemVerilog | |
GNU General Public License v3.0 or later | Apache License 2.0 |
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
XiangShan
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Loongson 3A6000: A Star Among Chinese CPUs
Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.
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MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).
You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...
Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.
> Perhaps they will provide compiler patches if required.
I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...
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Ask HN: Are there any open source dual-issue RISC-V processor
This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan
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How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
Maybe implement a big feature for a open source design? like vroom or xiangshan.
- 大炼芯运动彻底破产,跪舔韩国要技术
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New processor, OS to propel open-source chip ecosystem
I did know about XiangShan, but not Aolai. Is it a Linux distribution?
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
- Open-source high-performance RISC-V processor
ibex
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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Major Changes at RISC-V Designer SiFive
We've had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex.
An ETH Zurich team have done a triple core lockstep version for cubesats: https://www.theregister.com/2023/10/05/riscv_microcontroller...
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Hot Chips 2023: SiFive’s P870 Takes RISC-V Further
I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and it what matters.
However, RISCV cores abound. In pretty much any computing language known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time.
Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully.
https://github.com/lowRISC/ibex
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Looking to work in Open Source Silicon and RISC-V? lowRISC is hiring DV and infrastructure engineers
lowRISC's (www.lowrisc.org) mission is to bring open source silicon to the hardware world and see it shipping in volume in commercial applications. We want to see open source silicon occupy a similar position to open source software (e.g. look at Linux, it's the default choice in many applications, we'd like open source silicon to be used for similar foundational technologies in the hardware world).
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How to use verilator to transfer a design with multiple files to a verilated model?
Here I will just use Ibex, a risc-v processor as an example, of which the repository is here: lowrisc_ibex. There are many files in this repository and I wonder which files I need given a specific configuration (for example, the configuration of "maxperf"), and how I can combine all the necessary files together, feed them to verilator and get its verilated model? I understand that only by going through this step will I acquire necessary C++ header files to write the testbench
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Ushering In a New Era for Open-Source Silicon Development (CEO of lowrisc , a non profit that develops open source hardware on why open source hardware failed in the past, and how lowrisc does things differently)
i think it might be worth it to post it here because lowrisc develops ibex (a open source risc-v core).
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What is to be gained from ISA convergence on all levels of computing?
Yeah but you can have both an open source (e.g. ibex) and closed source implementations for controllers (the open source one is free and you can improve it and even close its source so competitors won't benefit from your improvements) , and you can migrate from one supplier to another without spending a lot of money on migrating the software.
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synthesizing and using the Ibex RISC-V core
I am pretty new to RISC-V and open-source hardware and just began learning and working with them as part of my research. I searched about different models that have some credible documents and research done into them and decided I would try and use the ibex as the hardware language is easier for me to follow too.
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RISC-V Pushes into the Mainstream
Ibex is open source and has taped out - https://github.com/lowRISC/ibex
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RISC-V simulator
That said we used Spike as a reference simulator for verifying Ibex (RISC-V core I work on, https://github.com/lowRISC/ibex) and we run an extensive set of random programs through it comparing its execution to Ibex's and I've not come across any major issues.
What are some alternatives?
openc910 - OpenXuantie - OpenC910 Core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
opentitan - OpenTitan: Open source silicon root of trust
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
tomverbeure
peakperf - Achieve peak performance on x86 CPUs and NVIDIA GPUs
riscv-isa-manual - RISC-V Instruction Set Manual
chisel - Chisel: A Modern Hardware Design Language
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
lowrisc-chip - The root repo for lowRISC project and FPGA demos.