XRT
Run Time for AIE and FPGA based platforms (by Xilinx)
Vitis-Tutorials
Vitis In-Depth Tutorials (by Xilinx)
| XRT | Vitis-Tutorials | |
|---|---|---|
| 1 | 4 | |
| 512 | 1,063 | |
| 0.2% | 2.6% | |
| 9.7 | 9.3 | |
| 2 days ago | 22 days ago | |
| C++ | C | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
XRT
Posts with mentions or reviews of XRT.
We have used some of these posts to build our list of alternatives
and similar projects.
Vitis-Tutorials
Posts with mentions or reviews of Vitis-Tutorials.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-19.
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
What are some alternatives?
When comparing XRT and Vitis-Tutorials you can also consider the following projects:
ZynqMP-FPGA-Linux - FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
finn-examples - Dataflow QNN inference accelerator examples on FPGAs