WARP_Core
BYU_PYNQ_PR_Video_Pipeline
| WARP_Core | BYU_PYNQ_PR_Video_Pipeline | |
|---|---|---|
| 2 | 2 | |
| 7 | 14 | |
| - | - | |
| 0.0 | 0.0 | |
| almost 4 years ago | over 5 years ago | |
| VHDL | Jupyter Notebook | |
| - | BSD 3-clause "New" or "Revised" License |
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WARP_Core
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Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
BYU_PYNQ_PR_Video_Pipeline
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
corundum - Open source FPGA-based NIC and platform for in-network compute
verilog-wishbone - Verilog wishbone components
fiate - Fault Injection Automatic Test Equipment
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images