Vitis_Accel_Examples
SoC
Vitis_Accel_Examples | SoC | |
---|---|---|
3 | 1 | |
467 | 11 | |
1.5% | - | |
8.0 | 1.1 | |
4 months ago | about 1 year ago | |
Makefile | VHDL | |
MIT License | - |
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Vitis_Accel_Examples
- Can you help me dataflow checking failure on vitis hls?
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How to Implement a decision tree on FPGA?
3- Then in Vitis I have implement that if-else statement to build the hardware. I have taken this Vitis hello world example as reference to write code for decision tree.
- Design AXI4 MM -> S and S -> MM
SoC
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I2C communication between Minized to arduino
You can have a look at this : https://github.com/cteqeu/Embedded-FPGA/tree/master/MiniZED/eFPGA_I2C_PS
What are some alternatives?
XRT - Run Time for AIE and FPGA based platforms
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
kvm-ip-zynq - KVM over IP Gateway targeting Zynq-7000 SoC
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
Vitis-Tutorials - Vitis In-Depth Tutorials
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
c8hardcaml - An implementation of a CHIP-8 machine for FPGAs in Hardcaml with a custom assembler for writing test programs
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog