VexRiscv VS linux-on-litex-vexriscv

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.

If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.

Something like https://github.com/SpinalHDL/VexRiscv will take far fewer

A CPU built around the Gentoo philosophy would look like https://github.com/SpinalHDL/VexRiscv ;). Don't want an MMU? Fine. Need a larger RAM interface? You got it. Barrel ALU for DSP? Sure.

Interpreted languages work by consolidating all of the optimization effort in the interpreter. This is similar to how CPUs work now, instead of extremely specific optimizations that are hard to create distributed among all code we use very general optimizations that push the limits of mathematics that is centralized in a CPU.

-----

Itanium had a lot of contemporary issues that made it not work. I would certainly blame Intel's business practices and reputation for a large part of it. There are likely niches for such processors. The VLIW is useful for DSP or graphics. Indeed, the only extant VLIW (that I know of) processor is the Russian Elbrus. I think the VLIW is only included to let them reuse a lot of the core logic of the CPU to drive a DSP engine, useful for radar and scientific simulation, though the sci sim would probably use commercial hardware which would be faster.

It works on GPUs because they're doing DSP, basically. We could have weirder topologies for GPUs however, like a massive string of ALUs driven off an embedded core, so you try to kachunk all your data in a single clock domain after configuring the ALU string.

4) https://github.com/SpinalHDL/VexRiscv

I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.

I'd recommend giving vexriscv a look. It'll handily fit on your FPGA, leaving plants of room for I2C, VGA output, and whatever multiplication you end up wanting to do. It's very easy to get set up, and their example "briey" SOC even has VGA output already, but not hardware I2C (though you could easily bitbang it with the core). Adding in I2C via a "plugin" should be trivial.

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

Hello, we are planning to rebuild a computer architectures course at uni and the idea is to teach the basics using the riscv architecture. We are looking for an affordable development board that could be used to demonstrate both bare-metal programming as well as interfacing hardware via mmap from OS to build up the experience with accessing the registers directly, and then introducing virtual memory, memory hierarchy, etc. So far it seems like a best option to utilize some compatible FPGA development board and the litex ( https://github.com/litex-hub/linux-on-litex-vexriscv ) project to achieve the afforementioned. Would you have any comment on that or perhaps some other recommendation for an affordable development board? Thanks for any tips.

The repo below has support for building a 32bit RISC-V CPU for de10nano. It also includes information about booting Linux.

https://github.com/litex-hub/linux-on-litex-vexriscv

The CPU will likely have a clock speed around 100Mhz, far slower than the 1.5Ghz 64bit cores on the VisionFive 2 or Pi4. The FPGA might still be useful if you want to customize the CPU or integrate other custom hardware.

You can run linux even on an entirely open source from hardware to software toolchain: https://github.com/litex-hub/linux-on-litex-vexriscv

On the other hand, if you really want a budget FPGA board under 100 USD that can implement a Linux-capable RISC-V SoC, you will need to implement a simple 32-bit one but indeed possible. See https://github.com/litex-hub/linux-on-litex-vexriscv for instance. You will get additional frequencies (still an order of 100 MHz though), I/O ports and such if you can spend 200 to 300 USD.

An Artix 7 100k (like in the 'big' Arty A7 board) will comfortably fit 4 VexRiscv @ 100 MHz in a Litex SoC with all the bells and whistles; you can already fit a SoC with 2 Vex in the smaller 35k. Running Linux on that is very easy.

Accessibility has improved significantly over the last few years. You can now buy any of the Lattice iCE40 or ECP5 boards from this page and use the yosys open-source workflow to upload real designs to the cores, including soft cores capable of running real, unmodified Linux. These tools are actively developed and are used by the open-source FPGA community at large (with the iCE40 and ECP5 receiving massive upticks in mindshare as a result).