SaxonSoc
SoC based on VexRiscv and ICE40 UP5K (by SpinalHDL)
litedram
Small footprint and configurable DRAM core (by enjoy-digital)
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SaxonSoc | litedram | |
---|---|---|
1 | 6 | |
141 | 356 | |
2.1% | - | |
4.8 | 6.6 | |
22 days ago | about 1 month ago | |
Scala | Python | |
MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
SaxonSoc
Posts with mentions or reviews of SaxonSoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-26.
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How many more years until we have a completely open source RISC-V SOC?
Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.
litedram
Posts with mentions or reviews of litedram.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-14.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.
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I am trying to avoid AXI Bus for DDR3 access on Arty A7
Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.
- LiteDRAM – A fully open-source memory controller targeting LPDDR4/5 for FPGA
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
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How many more years until we have a completely open source RISC-V SOC?
So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.
What are some alternatives?
When comparing SaxonSoc and litedram you can also consider the following projects:
litex - Build your hardware, easily!
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
SpinalHDL - Scala based HDL
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
litepcie - Small footprint and configurable PCIe core
hdcp
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
rocket-chip - Rocket Chip Generator
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
OpenSERDES - Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.