OpenFPGA
An Open-source FPGA IP Generator (by lnis-uofu)
hdl
HDL libraries and projects (by analogdevicesinc)
OpenFPGA | hdl | |
---|---|---|
3 | 5 | |
744 | 1,383 | |
2.2% | 2.3% | |
9.7 | 9.1 | |
6 days ago | 5 days ago | |
Verilog | Verilog | |
MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenFPGA
Posts with mentions or reviews of OpenFPGA.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-02-12.
- OpenFPGA. The future of video game preservation
-
Clear – The Open Source FPGA ASIC
Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.
hdl
Posts with mentions or reviews of hdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-01.
-
Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
-
Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library