HDL_Converter
cocotb-bus
| HDL_Converter | cocotb-bus | |
|---|---|---|
| 1 | 1 | |
| 5 | 46 | |
| - | - | |
| 0.0 | 3.7 | |
| about 2 years ago | 2 months ago | |
| C# | Python | |
| GNU Affero General Public License v3.0 | GNU General Public License v3.0 or later |
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HDL_Converter
cocotb-bus
-
Cocotb
The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.
What are some alternatives?
Symbolica - Symbolica's open-source symbolic execution engine. [Moved to: https://github.com/Symbolica/Symbolica]
cocotbext-axi - AXI interface modules for Cocotb
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
uLab-system-builder - This program generates project settings (such as pin assignments) and basic Verilog code for the μLab Kiwi FPGA development board
hdl_checker - Repurposing existing HDL tools to help writing better code
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
turbobus - TurboBus is an opinionated implementation of Command Responsibility Segregation pattern in python.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development