Compliance-Tests
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features (by VHDL)
surf
A huge VHDL library for FPGA development (by slaclab)
| Compliance-Tests | surf | |
|---|---|---|
| 1 | 1 | |
| 25 | 285 | |
| - | 1.1% | |
| 4.0 | 8.7 | |
| 6 days ago | 8 days ago | |
| VHDL | VHDL | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Compliance-Tests
Posts with mentions or reviews of Compliance-Tests.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-08.
-
VHDL Testbench Library Comparison
There is an initiative for feature support here: https://github.com/VHDL/Compliance-Tests/ but is has not been active for over a year. With a compliance test anyone can test their own simulator or simulators they are evaluating. A public comparison is trickier as such benchmarking is typically prohibited by the license.
surf
Posts with mentions or reviews of surf.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-18.
What are some alternatives?
When comparing Compliance-Tests and surf you can also consider the following projects:
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
chisel - Chisel: A Modern Hardware Design Language
tiny-cores - Collection of assorted small cores
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
fusesoc-cores - FuseSoC standard core library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
opentitan - OpenTitan: Open source silicon root of trust