verilog-hdl

Open-source projects categorized as verilog-hdl
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Language: + Python + VHDL + CMake + Swift + Propeller Spin
Topics: Fpga Python Compiler Verilog Hardware
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Top 6 verilog-hdl Open-Source Projects

  • vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

  • Pyverilog

    Python-based Hardware Design Processing Toolkit for Verilog HDL

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • nngen

    NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

  • FakePGA

    Simulating Verilog designs on a microcontroller

  • Fault

    A complete open-source design-for-testing (DFT) Solution

  • jcap

    JAMMA Custom Arcade Project

    • Project mention: UPDATED - 2-Layer THT PCB/Schematic Review Request | /r/PrintedCircuitBoard | 2023-09-20

    You can also find the KiCAD project here.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

verilog-hdl related posts

  • Tools for designing hardware in Python

    6 projects | /r/Python | 26 Mar 2022

  • Tools for DFT

    1 project | /r/vlsi | 4 Jul 2021

  • How to compare HDL simulation/implementation results to Matlab?

    6 projects | /r/FPGA | 1 Jun 2021

Index

What are some of the best open-source verilog-hdl projects? This list will help you:

Project Stars
1 vunit 684
2 Pyverilog 575
3 nngen 319
4 FakePGA 152
5 Fault 116
6 jcap 12

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