ghdl

Open-source projects categorized as ghdl
Edit details
Language: + VHDL + Python + Verilog + PHP
Topics: Vhdl Fpga Verilog Xilinx Simulation
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured

Top 10 ghdl Open-Source Projects

  • ghdl

    VHDL 2008/93/87 simulator

  • edalize

    An abstraction library for interfacing EDA tools

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • hdl_checker

    Repurposing existing HDL tools to help writing better code

  • spi-fpga

    SPI master and SPI slave for FPGA written in VHDL

  • uart-for-fpga

    Simple UART controller for FPGA written in VHDL

  • neorv32-setups

    📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

    • Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

    Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

  • neorv32-verilog

    ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

    SaaSHub logo

  • neorv32-riscof

    ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

  • parvaj

    Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

  • upduino-projects

    Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

ghdl related posts

  • GHDL on mac m1

    2 projects | /r/VHDL | 30 Mar 2023

  • How to compile ghdl

    1 project | /r/FPGA | 23 Jan 2023

  • Is the VHDL standard library not publicly available?

    2 projects | /r/VHDL | 15 Dec 2022

  • Help on trying to find a FOSS solution to replace Quartus in my class.

    2 projects | /r/FPGA | 15 Nov 2022

  • If someone is good at programming languages like C, will they be good at description languages like VHDL?

    1 project | /r/ElectricalEngineering | 29 Oct 2022

  • What is the netlist file format?

    1 project | /r/VHDL | 27 Oct 2022

  • Converting VHDL to Verilog using GHDL

    2 projects | /r/VHDL | 10 Oct 2022
  • A note from our sponsor - SaaSHub
    www.saashub.com | 21 May 2024
    SaaSHub helps you find the best software and product alternatives Learn more →

Index

What are some of the best open-source ghdl projects? This list will help you:

Project Stars
1 ghdl 2,232
2 edalize 596
3 hdl_checker 184
4 spi-fpga 157
5 uart-for-fpga 89
6 neorv32-setups 53
7 neorv32-verilog 40
8 neorv32-riscof 24
9 parvaj 12
10 upduino-projects 6

Sponsored
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com