SDR SDRAM Controller in Verilog (MT48LC16M16)

• arrowzip

  3 19 0.0 Verilog

  A ZipCPU based demonstration of the MAX1000 FPGA board

If it would help, here are two SDRAM controllers: The first is for a winbond W9825G6JH (4M x 4 banks x 16 bits). It was designed for the XuLA-LX25 FPGA board, although it also works on my MAX-1000 board from Arrow as well. Beware, the clock needs to be offset 90 degrees from the data. The second controller works on an ISSI IS42S16100H/IS45S16100H SDRAM. Both use Wishbone (pipeline) interfaces. If you aren't using Wishbone, you might need a converter to ... whatever bus protocol you are using.

• axi_softcores

  1 0 0.0 Verilog

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