lowRISC stopped working on their SoC in 2018 ;-(

• lowrisc-chip

  1 584 2.4 SystemVerilog

  The root repo for lowRISC project and FPGA demos.

  

• opentitan

  14 2,357 10.0 SystemVerilog

  OpenTitan: Open source silicon root of trust

  

Whilst the 64-bit SoC project isn't being actively developed we are working hard on OpenTitan (https://opentitan.org/, https://github.com/lowRISC/opentitan) which we hope will become the first large scale deployment of significant open source silicon IP.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• ibex

  20 1,244 8.3 SystemVerilog

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

Our RISC-V core, Ibex (https://github.com/lowRISC/ibex) continues to be developed, I recently updated our testbench to use step by step co-simulation with Spike, which you can run in either VCS or with Verilator (so allowing a fully open source verification option). It will be used in OpenTitan and we've had multiple companies let us know they've been using it various things (e.g. Wavious: https://github.com/waviousllc/wav-lpddr-hw/tree/main/rtl/ibex).

• wav-lpddr-hw

  2 87 3.2 SystemVerilog

  Wavious DDR (WDDR) Physical interface (PHY) Hardware

  

Our RISC-V core, Ibex (https://github.com/lowRISC/ibex) continues to be developed, I recently updated our testbench to use step by step co-simulation with Spike, which you can run in either VCS or with Verilator (so allowing a fully open source verification option). It will be used in OpenTitan and we've had multiple companies let us know they've been using it various things (e.g. Wavious: https://github.com/waviousllc/wav-lpddr-hw/tree/main/rtl/ibex).

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