RISC-V IP core on an FPGA.

• picorv32

  15 2,770 5.2 Verilog

  PicoRV32 - A Size-Optimized RISC-V CPU

  

While I have to believe there exists a RISC-V core with a good, fast, and working AXI interface, they're unfortunately hard to find. VexRiscv's AXI interface was quite broken when I last examined it. PicoRV's AXI interface should work, but it's nothing to write about. Although PICORV32 is supposed to be able to run at 250MHz, that bus interface is going to cost you a minimum of about 10 clocks per access. See here, Fig 13 for example. Since the PICORV32 uses the same interface for both instruction fetch and memory, you'll likely require 10-20 cycles per instruction for the memory access alone. Add another (rough) 20 cycles per instruction if your CPU is running from DDR3 SDRAM.

• Taiga

  1 - -

The Taiga is my favorite so far, is a little complicated to implement. https://gitlab.com/sfu-rcl/Taiga

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

Suggest a related project