Resources for converting FPGA design to ASIC/VLSI

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
asic-design Asic 130nm Magic netgen

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  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    • Check out Open Lane and the Sky Water pdk. Skywater is an open source asic cell library, open lane is an example project going from Verilog to gds (asic layout) using skywater. Skywater behavioral files come in Verilog form.

  • InfluxDB

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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