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InfluxDB
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Kinda, sorta? This is like saying "a computer is not enough, you need a binary." What's here is the source code in Verilog. This produces a netlist (set of gates) which is synthesized into an actual bitstream (proprietary gate configuration file) for a specific FPGA hosted on a specific board.
In this case, the project isn't very documented but it looks like fairly generic Verilog without a lot of vendor specific extensions. So, what you need is a Verilog toolchain which can synthesize the source code into a netlist, and then into a bitstream, and the right set of extra code to target an actual physical piece of hardware.
Right now, it looks like the only board support that's checked into the repository is for the Icarus Verilog simulation environment: https://github.com/nukeykt/Nuked-MD-FPGA/tree/main/icarus .
But, the overall setup looks pretty simple and generic, so it should (hopefully) be possible to synthesize to your board of choice by reimplementing run.v and memstubs.v towards an actual hardware configuration.
But there already exist cores for Mister and Analogue Pocket. e.g. https://github.com/MiSTer-devel/Genesis_MiSTer
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