xv6-public VS picorv32

+1 for mini operating system.

Us, application developers, rely on many OS features: memory management, filesystem, etc. I'm sure eventually we'll ask "how such things are done behind the scene?"

That's why I tinker with xv6 (https://github.com/mit-pdos/xv6-public) during sparetime. Learning various process scheduling algorithms from textbook is a thing. Implementing it is another thing. I learn a lot. And it's definitely fun, even though there's almost zero chance the knowledge gained is relevant for my job (I'm a mobile app dev).

Recently I compiled xv6 using gcc 7.5.0 on Ubuntu 18 , everything is ok. But when I try to compile it using gcc 13.2.1 on latest Arch, it's failed: result

https://github.com/mit-pdos/xv6-public has under 10,000 lines of C and assembly including some user space programs.

xv6 was originally written for 32-bit x86; the RISC-V port is a relatively recent development. See e.g. https://github.com/mit-pdos/xv6-public for some of the earlier history.

rxv64 was written for a specific purpose: we had to ramp up professional engineers on both 64-bit x86_64 and kernel development in Rust; we were pointing them to the MIT materials, which at the time still focused on x86, but they were getting tripped up 32-bit-isms and the original PC peripherals (e.g., accessing the IDE disk via programmed IO). Interestingly, the non sequitur about C++ aside, porting to Rust exposed several bugs or omissions in the C original; fixes were contributed back to MIT and applied to the original (and survived into the RISC-V port).

Oh, by the way, the use of the term "SMP" predates Intel's usage by decades.

I'd define an arena as the pattern where the arena itself owns N objects. So you free the arena to free all objects.

My first job was at EA working on console games (PS2, GameCube, XBox, no OS or virtual memory on any of them), and while at the time I was too junior to touch the memory allocators themselves, we were definitely not malloc-ing and freeing all the time.

It was more like you load data for the level in one stage, which creates a ton of data structures, and then you enter a loop to draw every frame quickly. There were many global variables.

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Wikipedia calls it a region, zone, arena, area, or memory context, and that seems about right:

https://en.wikipedia.org/wiki/Region-based_memory_management

It describes history from 1967 (before C was invented!) and has some good examples from Apache ("pools") and Postgres ("memory contexts").

I also just looked at these codebases:

https://github.com/mit-pdos/xv6-public (based on code from the 70's)

https://github.com/id-Software/DOOM (1997)

I looked at allocproc() in xv6, and gives you an object from a fixed global array. A lot of C code in the 80's and 90's was essentially "kernel code" in that it didn't have an OS underneath it. Embedded systems didn't run on full-fledges OSes.

DOOM tends to use a lot of what I would call "pools" -- arrays of objects of a fixed size, and that's basically what I remember from EA.

Though in g_game.c, there is definitely an arena of size 0x20000 called "demobuffer". It's used with a bump allocator.

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So I'd say

- malloc / free of individual objects was NEVER what C code looked like (aside from toy code in college)

- arena allocators were used, but global vars and pools are also very common.

- arenas are more or less wash for memory safety. they help you in some ways, but hurt you in others.

The reason C programmers don't malloc/free all the time is for speed, not memory safety. Arenas are still unsafe.

When you free an arena, you have no guarantee there's nothing that points to it anymore.

Also, something that shouldn't be underestimated is that arena allocators break tools like ASAN, which use the malloc() free() interface. This was underscored to me by writing a garbage collector -- the custom allocator "broke" ASAN, and that was actually a problem:

https://www.oilshell.org/blog/2023/01/garbage-collector.html

If you want memory safety in your C code, you should be using ASAN (dynamically instrumented allocators) and good test coverage. Arenas don't help -- they can actually hurt. An arena is a trivial idea -- the problem is more if that usage pattern actually matches your application, and apps evolve over time.

Magma is proudly licensed under the MIT license, and uses code from Xv6 and Yagura.

My OS classes used xv6, a reimplementation of Unix Version 6 for a RISC-V architecture. Accompanying that was the OSTEP textbook.

Check out xv6 if you are only getting started with operating systems and want something simpler.

Here is kernel.ld.

> Right now, most devices on the market do not support the C extension

This is not true and easily verifiable.

The C extension is defacto required, the only cores that don't support it are special purpose soft cores.

C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file

Supports M and C extensions https://github.com/YosysHQ/picorv32

Another sized optimized core with C extension support https://github.com/lowrisc/ibex

C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html

This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax

In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v

The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.

Picorv32: https://github.com/YosysHQ/picorv32

There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32

picorv32 is written in Verilog.

In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

That is, reducing the number of LUT required to implement a CPU of a given ISA.

A basic RV32 CPU is down to 500-700 LUT.

    https://github.com/YosysHQ/picorv32

I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.

Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32