uart-for-fpga
wb_spi_bridge
uart-for-fpga | wb_spi_bridge | |
---|---|---|
1 | 2 | |
89 | 19 | |
- | - | |
0.0 | 0.0 | |
almost 3 years ago | over 2 years ago | |
VHDL | VHDL | |
MIT License | BSD 3-clause "New" or "Revised" License |
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uart-for-fpga
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Entity bound SDC in Quartus
The code in the link below contains an example of my use of the altera_attribute: https://github.com/jakubcabal/uart-for-fpga/blob/master/examples/common/rst_sync.vhd
wb_spi_bridge
What are some alternatives?
fpu - IEEE 754 floating point library in system-verilog and vhdl
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
sdram-fpga - A FPGA core for a simple SDRAM controller.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
cyc1000-rsu - The CYC1000 FPGA Remote System Upgrade project
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.