uart-for-fpga
fpu
uart-for-fpga | fpu | |
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1 | 1 | |
89 | 47 | |
- | - | |
0.0 | 6.2 | |
almost 3 years ago | 5 days ago | |
VHDL | VHDL | |
MIT License | Apache License 2.0 |
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uart-for-fpga
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Entity bound SDC in Quartus
The code in the link below contains an example of my use of the altera_attribute: https://github.com/jakubcabal/uart-for-fpga/blob/master/examples/common/rst_sync.vhd
fpu
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High level floating point arithmetic in vhdl
Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.
What are some alternatives?
sdram-fpga - A FPGA core for a simple SDRAM controller.
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
cyc1000-rsu - The CYC1000 FPGA Remote System Upgrade project
fpu-sp - IEEE 754 floating point library in system-verilog and vhdl
or1200 - OpenRISC 1200 implementation
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
VHDL-Guide - VHDL Guide
edalize - An abstraction library for interfacing EDA tools
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.