uart-for-fpga VS cyc1000-rsu

Compare uart-for-fpga vs cyc1000-rsu and see what are their differences.

uart-for-fpga

Simple UART controller for FPGA written in VHDL (by jakubcabal)
Uart Fpga uart-controller Vhdl Controller wishbone wishbone-bus uart-loopback Simulation ghdl cyc1000
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cyc1000-rsu

The CYC1000 FPGA Remote System Upgrade project (by jakubcabal)
Fpga Vhdl cyc1000 bitstream-update rsu cyclone10lp Uart
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uart-for-fpga cyc1000-rsu
1 1
89 7
- -
0.0 4.1
almost 3 years ago almost 3 years ago
VHDL VHDL
MIT License MIT License
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uart-for-fpga

Posts with mentions or reviews of uart-for-fpga. We have used some of these posts to build our list of alternatives and similar projects.
  • Entity bound SDC in Quartus
    1 project | /r/FPGA | 23 Apr 2022
    The code in the link below contains an example of my use of the altera_attribute: https://github.com/jakubcabal/uart-for-fpga/blob/master/examples/common/rst_sync.vhd

cyc1000-rsu

Posts with mentions or reviews of cyc1000-rsu. We have used some of these posts to build our list of alternatives and similar projects.
  • Intel Cyclone 10 LP update from serial comm
    1 project | /r/FPGA | 28 Jun 2022
    Hi, there is my solution of CYC1000 (Cyclone 10 LP board) Remote System Upgrade. The first implementation allows remote bitstream updates via the UART interface. https://github.com/jakubcabal/cyc1000-rsu

What are some alternatives?

When comparing uart-for-fpga and cyc1000-rsu you can also consider the following projects:

fpu - IEEE 754 floating point library in system-verilog and vhdl

forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL

sdram-fpga - A FPGA core for a simple SDRAM controller.

uart-for-fpga vs fpu cyc1000-rsu vs forth-cpu uart-for-fpga vs sdram-fpga