lion
VELDT-getting-started
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| lion | VELDT-getting-started | |
|---|---|---|
| 10 | 2 | |
| 242 | 21 | |
| 0.8% | - | |
| 4.5 | 3.0 | |
| 5 days ago | 4 months ago | |
| Haskell | Haskell | |
| BSD 3-clause "New" or "Revised" License | MIT License |
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lion
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A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
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C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
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Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
- Lion is a formally verified, 5-stage pipeline RISC-V core
- Lion: A formally verified, 5-stage pipeline RISC-V core
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Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
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Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
VELDT-getting-started
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Where Lions Roam: RISC-V on the VELDT
Absolutely! I have also written a guide to getting started with Clash and the VELDT. It starts with a basic counter and builds incrementally to a UART. Definitely check out the Clash website for examples, documentation, tutorials, and blog posts! The Clash website is my go-to resource.
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Linear types for circuit design in Haskell/Clash
In terms of not just code, but also text, https://github.com/standardsemiconductor/VELDT-getting-started is a really great tutorial
What are some alternatives?
prometheus-cpp - Prometheus Client Library for Modern C++
clash-spaceinvaders - Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
riscv-formal - RISC-V Formal Verification Framework
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
contranomy
atomic-story - Understanding how atomics and memory ordering work
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
libcxx - Project moved to: https://github.com/llvm/llvm-project
wit - WIT (Wikipedia-based Image Text) Dataset is a large multimodal multilingual dataset comprising 37M+ image-text sets with 11M+ unique images across 100+ languages.
iele-semantics - Semantics of Virtual Machine for IELE prototype blockchain