soft_riscv
Soft-core RISCV processor for RISCV 2018 competition (by AEW2015)
xfcp
Extensible FPGA control platform (by alexforencich)
Our great sponsors
| soft_riscv | xfcp | |
|---|---|---|
| 1 | 5 | |
| 4 | 51 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | 12 months ago | |
| C | Verilog | |
| - | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
soft_riscv
Posts with mentions or reviews of soft_riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
xfcp
Posts with mentions or reviews of xfcp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Ethernet PC-FPGA interface
This is exactly what I created https://github.com/alexforencich/xfcp for - Ethernet and serial to multiple internal components, with the ability to enumerate said components.
-
Options for control and configuration of FPGA from PC
This is basically what I made XFCP for: https://github.com/alexforencich/xfcp
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .
-
FPGA development live stream: FPGA board bring-up and testing of high-speed serializers
I'll use my XFCP project to interface with the FPGA from Python via a USB serial chip. This provides access to the I2C bus on the board, for configuring the PLL chips and interfacing with the QSFP28 optical transceivers. Additionally, it connects to the dynamic reconfiguration ports (DRP) on the GTY transceivers, and I'll use that for performing BER measurements at 25 Gbps through a handful of QSFP28 cables and optical modules. It looks like I might also have to do some fine-tuning of some of the analog parameters on the transceivers (namely pre-emphasis).
-
FPGA development live stream: FPGA board bring-up and testing
I recently acquired a pair of rather large FPGA boards that have a bunch of high-speed IO. I figure it might be interesting to show the process for bringing them up in terms of the reference clock generation and distribution components on the board for the high-speed serializers, as well as performing some simple sanity checks (BER testing) on all of the interfaces to make sure everything is operational. I'll use my XFCP project to interface with the FPGA from Python for configuring the clocking components over I2C and for performing the BER measurements on the GTY transceivers via DRP.
What are some alternatives?
When comparing soft_riscv and xfcp you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
verilog-wishbone - Verilog wishbone components
litex - Build your hardware, easily!
corundum - Open source FPGA-based NIC and platform for in-network compute