sleighcraft VS Surelog

Compare sleighcraft vs Surelog and see what are their differences.

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
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sleighcraft Surelog
1 1
245 330
0.0% 2.7%
0.0 9.4
over 2 years ago 2 months ago
C++ C++
Apache License 2.0 Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

sleighcraft

Posts with mentions or reviews of sleighcraft. We have used some of these posts to build our list of alternatives and similar projects.

Surelog

Posts with mentions or reviews of Surelog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-02-05.

What are some alternatives?

When comparing sleighcraft and Surelog you can also consider the following projects:

Triton - Triton is a dynamic binary analysis library. Build your own program analysis tools, automate your reverse engineering, perform software verification or just emulate code.

verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

pharos - Automated static analysis tools for binary programs

slang - SystemVerilog compiler and language services

mcsema - Framework for lifting x86, amd64, aarch64, sparc32, and sparc64 program binaries to LLVM bitcode

naja-verilog - A standalone structural (gate-level) verilog parser

LIEF - LIEF - Library to Instrument Executable Formats

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

rz-ghidra - Deep ghidra decompiler and sleigh disassembler integration for rizin

f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.