simple-c-compiler VS Pyverilog

Compare simple-c-compiler vs Pyverilog and see what are their differences.

simple-c-compiler

Simple C Compiler written in Python (by Hyper5phere)
Python Lexer Parser Code-Generator semantic-analyzer Compiler from-scratch Interpreter Blog
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Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL (by PyHDI)
verilog-hdl Hardware Compiler Parser dataflow-analyzer control-flow-analyzer Code-Generator Python
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simple-c-compiler Pyverilog
1 2
49 571
- 3.7%
10.0 0.0
over 1 year ago 9 months ago
Python Python
MIT License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

simple-c-compiler

Posts with mentions or reviews of simple-c-compiler. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-09-14.

Pyverilog

Posts with mentions or reviews of Pyverilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-26.
  • Tools for designing hardware in Python
    6 projects | /r/Python | 26 Mar 2022
    Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    PyVerilog https://github.com/PyHDI/Pyverilog

What are some alternatives?

When comparing simple-c-compiler and Pyverilog you can also consider the following projects:

ncndi - MPL Programming Language: an interpreted programming language by Dante Falzone

pyverilator - Python wrapper for verilator model

miss_hit - MATLAB Independent, Small & Safe, High Integrity Tools - code formatter and more

myhdl - The MyHDL development repository

front - Front-end libraries and utilities for the Transmuter language processing infrastructure

PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.

cinder - Cinder is Meta's internal performance-oriented production version of CPython.

datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.

blog-publishing - 🚀 Automated blog publishing from Hashnode to Medium and Dev.to.

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

CaptCC - A tiny C compiler written purely in JavaScript.

nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

simple-c-compiler vs ncndi Pyverilog vs pyverilator simple-c-compiler vs miss_hit Pyverilog vs myhdl simple-c-compiler vs front Pyverilog vs PyRTL simple-c-compiler vs cinder Pyverilog vs datamodel-code-generator simple-c-compiler vs blog-publishing Pyverilog vs nmigen simple-c-compiler vs CaptCC Pyverilog vs nngen