riscv-tests
highway
riscv-tests | highway | |
---|---|---|
9 | 66 | |
783 | 3,645 | |
2.3% | 1.8% | |
7.5 | 9.8 | |
about 18 hours ago | 7 days ago | |
C | C++ | |
GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-tests
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Computerraria: A fully compliant RISC-V computer inside Terraria
Fully compliant to RISC-V how? Is it conforming to a specific RVI profile? The project states "By emulating a complete rv32i instruction set inside the wiring system of Terraria, we push back speeds to the early 70s era, tossing the ball firmly back into the court of silicon engineer without losing any software functionality."
So this is building a RISC-V *microcontroller* but what version of the ISA? 2.2 from 2017? Is it sucessfully passing conformance tests (https://github.com/riscv-software-src/riscv-tests)? I don't want to dunk on the project, but the title is over-selling and not scoping the context of the work. I look forward to some more updates from @misprit7!
Note: I'm the working group lead for distro-integration within the RISC-V Software Ecosystem (RISE) group.
- Verification
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
- Efficient Way To Generate Test Benches For MIPS Processor?
- We need some support
- Available (official) test suite?
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Compliance tests official repository
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
highway
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Llamafile 0.7 Brings AVX-512 Support: 10x Faster Prompt Eval Times for AMD Zen 4
The bf16 dot instruction replaces 6 instructions: https://github.com/google/highway/blob/master/hwy/ops/x86_12...
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JPEG XL and the Pareto Front
[0] for those interested in Highway.
It's also mentioned in [1], which starts off
> Today we're sharing open source code that can sort arrays of numbers about ten times as fast as the C++ std::sort, and outperforms state of the art architecture-specific algorithms, while being portable across all modern CPU architectures. Below we discuss how we achieved this.
[0] https://github.com/google/highway
[1] https://opensource.googleblog.com/2022/06/Vectorized%20and%2..., which has an associated paper at https://arxiv.org/pdf/2205.05982.pdf.
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Gemma.cpp: lightweight, standalone C++ inference engine for Gemma models
Thanks so much!
Everyone working on this self-selected into contributing, so I think of it less as my team than ... a team?
Specifically want to call out: Jan Wassenberg (author of https://github.com/google/highway) and I started gemma.cpp as a small project just a few months ago + Phil Culliton, Dan Zheng, and Paul Chang + of course the GDM Gemma team.
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From slow to SIMD: A Go optimization story
C++ users can enjoy Highway [1].
[1] https://github.com/google/highway/
- GDlog: A GPU-Accelerated Deductive Engine
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Designing a SIMD Algorithm from Scratch
At that point it is better to have some kind of DSL that should not be in the main language, because it would target a much lower level than a typical program. The best effort I've seen in this scene was Google's Highway [1] (not to be confused with HighwayHash) and I even once attempted to recreate it in Rust, but it is still distanced from my ideal.
[1] https://github.com/google/highway
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SIMD Everywhere Optimization from ARM Neon to RISC-V Vector Extensions
Interesting, thanks for sharing :)
At the time we open-sourced Highway, the standardization process had already started and there were some discussions.
I'm curious why stdlib is the only path you see to default? Compare the activity level of https://github.com/VcDevel/std-simd vs https://github.com/google/highway. As to open-source usage, after years of std::experimental, I see <200 search hits [1], vs >400 for Highway [2], even after excluding several library users.
But that aside, I'm not convinced standardization is the best path for a SIMD library. We and external users extend Highway on a weekly basis as new use cases arise. What if we deferred those changes to 3-monthly meetings, or had to wait for one meeting per WD, CD, (FCD), DIS, (FDIS) stage before it's standardized? Standardization seems more useful for rarely-changing things.
1: https://sourcegraph.com/search?q=context:global+std::experim...
2: https://sourcegraph.com/search?q=context:global+HWY_NAMESPAC...
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Permuting Bits with GF2P8AFFINEQB
Thanks for the link. We were previously using GFNI for bit reversal and 8-bit shifts, and I just extended that to our 8-bit BroadcastSignBit (https://github.com/google/highway/pull/1784).
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Six times faster than C
You could study Google's Highway library [1].
[1] https://github.com/google/highway
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AMD EPYC 97x4 “Bergamo” CPUs: 128 Zen 4c CPU Cores for Servers, Shipping Now
Runtime feature detection need not be rare nor hard, it's a few dozen lines of boilerplate. You can even write your code just once: see https://github.com/google/highway#examples.
What are some alternatives?
riscv-arch-test
xsimd - C++ wrappers for SIMD intrinsics and parallelized, optimized mathematical functions (SSE, AVX, AVX512, NEON, SVE))
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
Vc - SIMD Vector Classes for C++
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
swup - Versatile and extensible page transition library for server-rendered websites 🎉
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
DirectXMath - DirectXMath is an all inline SIMD C++ linear algebra library for use in games and graphics apps
riscof
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
jpeg-xl