riscv-profiles
rpi-open-firmware
riscv-profiles | rpi-open-firmware | |
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21 | 12 | |
87 | 416 | |
- | 0.2% | |
8.0 | 4.4 | |
19 days ago | 3 months ago | |
Makefile | C | |
Creative Commons Attribution 4.0 | GNU General Public License v3.0 or later |
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riscv-profiles
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How to improve the RISC-V specification
Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.
https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...
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Raspberry Pi receives strategic investment from Arm
>there are a lot of incompatible ISA implementations of RISC-V
This is common FUD.
In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.
So do Linux distributions.
0. https://github.com/riscv/riscv-profiles/releases
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You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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The legend of "x86 CPUs decode instructions into RISC form internally"
That's why we have RISC-V profiles.
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Why is std::hardware_destructive_interference_size a compile-time constant instead of a run-time value?
Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.
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RISC-V Profiles: Defining sets of extensions for coherent ecosystems
The Profiles spec which includes RVA22 was finally ratified[0] last week.
0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0
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RISC-V Profiles
Context: RISC-V profiles spec got ratified last week.
- Questions about standard extensions
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RISC-V Business: Testing StarFive's VisionFive 2 SBC
Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.
But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:
https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
The 22 indicates the year.
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TinyEMU – x86 and RISC-V emulator, small and simple while being complete
Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
rpi-open-firmware
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Raspberry Pi receives strategic investment from Arm
> Please correct me if I'm wrong.
My memory told me it was the GPU that needed the blobs. So I asked at DDG
https://duckduckgo.com/?t=ftsa&q=binary+blobs+and+the+Raspbe...
Turned up this: https://wiki.debian.org/RaspberryPi and it says...
> All Raspberry Pi models before the 4 (1A, 1B, 1A+, 1B+, Zero, Zero W, 2, 3, Zero 2 W) boot from their GPU (not from the CPU!), so they require a non-free binary blob to boot
So the 4 (and I suppose the 5, if it ever actually comes...)
Goes on to say:
> Since then, Broadcom publicly released some code, licensed as 3-Clause BSD, to aid the making of an open source GPU driver. The "rpi-open-firmware" effort to replace the VPU firmware blob started in 2016. See more at https://news.ycombinator.com/item?id=11703842 . Unfortunately development of rpi-open-firmware is currently (2021-06) stalled.
So there you are. Not wrong, are you, but not strictly correct, depending on "...to run properly" definition
https://github.com/librerpi/rpi-open-firmware has updates 3-months ago
- LibreRPi – open source replacements for RPi firmware
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How is the free firmware for the Raspberry progressing?
many of those demos work on the the entire pi model range
pi3 support is only broken due to arm side problems, which could be fixed by just using a different bootloader
and the https://github.com/librerpi/rpi-open-firmware codebase can already boot linux headlessly on both pi2 and pi3, it uses a different arm bootloader
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Arduino Pro hardware is not open-source hardware
Yes, and some folks are reverse engineering their stuff:
https://github.com/librerpi/rpi-open-firmware/
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Hacker News top posts: Feb 25, 2021
rpi-open-firmware: open-source VPU side bootloader for Raspberry Pi\ (35 comments)
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rpi-open-firmware: open-source VPU side bootloader for Raspberry Pi
There is work being done on the RPi4, for example the SHA1 HMAC protecting the boot on the RPi4 had to be cracked (and was easily), I hear future versions have RSA signing support, so the proprietary firmware might become mandatory at some point.
https://github.com/librerpi/rpi-open-firmware/blob/master/do...
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AArch64 Boards and Perception
There is a project to create an open source version of the proprietary GPU firmware that boots into the ARM processor:
https://github.com/librerpi/rpi-open-firmware
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Taking a Stand in the War on General-Purpose Computing
I note that even the Raspberry Pi is moving towards locked down devices, the RPi4 has an (easily cracked) HMAC blocking booting into the open source firmware and I hear more recent hardware editions have RSA signing support in the bootrom code.
https://github.com/librerpi/rpi-open-firmware/blob/master/do...
What are some alternatives?
riscv-platform-specs - RISC-V Profiles and Platform Specification
OpenBBTerminal - Investment Research for Everyone, Everywhere.
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
tl - The compiler for Teal, a typed dialect of Lua
openc906 - OpenXuantie - OpenC906 Core
PrawnOS - Libre Mainline Kernel and Debian for arm laptops
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
lk-overlay
volk - The Vector Optimized Library of Kernels
serverlessui - A command-line utility for deploying serverless applications to AWS. Complete with custom domains, deploy previews, TypeScript support, and more.
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
java-keyring - Copy of Java Keyring library from bitbucket.org/bpsnervepoint -- with working CI in for osx/linux/windows keystore.