riscv-profiles
VisionFive2
riscv-profiles | VisionFive2 | |
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21 | 12 | |
87 | 423 | |
- | 1.2% | |
8.0 | 6.3 | |
19 days ago | 19 days ago | |
Makefile | Makefile | |
Creative Commons Attribution 4.0 | - |
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riscv-profiles
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How to improve the RISC-V specification
Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.
https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...
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Raspberry Pi receives strategic investment from Arm
>there are a lot of incompatible ISA implementations of RISC-V
This is common FUD.
In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.
So do Linux distributions.
0. https://github.com/riscv/riscv-profiles/releases
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You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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The legend of "x86 CPUs decode instructions into RISC form internally"
That's why we have RISC-V profiles.
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Why is std::hardware_destructive_interference_size a compile-time constant instead of a run-time value?
Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.
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RISC-V Profiles: Defining sets of extensions for coherent ecosystems
The Profiles spec which includes RVA22 was finally ratified[0] last week.
0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0
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RISC-V Profiles
Context: RISC-V profiles spec got ratified last week.
- Questions about standard extensions
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RISC-V Business: Testing StarFive's VisionFive 2 SBC
Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.
But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:
https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
The 22 indicates the year.
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TinyEMU – x86 and RISC-V emulator, small and simple while being complete
Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
VisionFive2
- What's the best board for novel OS development in terms of cost and quality of documentation?
- Release VisionFive2 Software v3.0.4 · starfive-tech/VisionFive2
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Haiku on VisionFive 2
booted from your SD wget https://github.com/starfive-tech/VisionFive2/releases/download/VF2_v2.11.5/u-boot-spl.bin.normal.out wget https://github.com/starfive-tech/VisionFive2/releases/download/VF2_v2.11.5/visionfive2_fw_payload.img flashcp -Av u-boot-spl.bin.normal.out /dev/mtd0 flashcp -Av visionfive2_fw_payload.img /dev/mtd1
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[LTT] I Can Save You Money! – Raspberry Pi Alternatives
Much of required support things for RISC-V SBC's across the board are incomplete/missing in mainline Linux device tree. VF2 is better than most random ARM SBC boards though, and there are efforts to upstream/mainline. RISC-V SBCs are just too new as a product category for mainline support to be possible quite yet. StarFive are open about this and the checklists/efforts going on: https://github.com/starfive-tech/linux/tree/visionfive and https://github.com/starfive-tech/VisionFive2
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VisionFive2 Hands-on Review
You can use this image to update by connecting through ssh: https://github.com/starfive-tech/VisionFive2/releases/download/VF2_v2.5.0/sdcard.img
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8GiB of RAM on VisionFive2 board
FWIW, there was new firmware released on Jan. 20: https://github.com/starfive-tech/VisionFive2/releases/tag/VF2_v2.8.0
- Has a detailed VisionFive-2 Memory Map and/or Register Explanation Been Release?
- RISC-V SBC VisionFive 2 Officially Shipped
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How do I get started with Vision Five 2 SBC?
Or you can try to build it yourself: https://github.com/starfive-tech/VisionFive2
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Anyone managed to create a bootable SD card image for the VisionFive 2?
I presume you've already seen issue 5 regarding the GPU driver files.
What are some alternatives?
riscv-platform-specs - RISC-V Profiles and Platform Specification
Fedora_on_StarFive
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
bl_iot_sdk - BL602/BL702 SDK. Any technical topic, please access the following link.
openc906 - OpenXuantie - OpenC906 Core
linux
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
volk - The Vector Optimized Library of Kernels
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
riscv-code-size-reduction
openc910 - OpenXuantie - OpenC910 Core