riscv-elf-psabi-doc
lz4_rv32i_decode
| riscv-elf-psabi-doc | lz4_rv32i_decode | |
|---|---|---|
| 11 | 1 | |
| 633 | 9 | |
| 1.7% | - | |
| 7.1 | 0.0 | |
| 10 days ago | about 2 years ago | |
| Python | Assembly | |
| Creative Commons Attribution 4.0 | BSD 3-clause "New" or "Revised" License |
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riscv-elf-psabi-doc
- ARM64EC (and ARM64X) Explained
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Lazarus IDE 3.0 Released
Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...
It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields.
It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks
- Please help!
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RISC-V assembler input file format
This one has more info on the ELF output, notably things like how things like relocations and special symbols like %pcrel_hi work: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
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RISC-V assembly example: incrementing each char in a string
This is a bit dense but that's what I referred to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc. I'm not sure if there's a RISC-V specific assembly tutorial that talks about calling conventions.
- RISCV on the rise. Intel joins the bandwagon. Threat or potential for linux gaming?
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RV32I Stack and stack pointer in hardware implementation
The stack is defined by the ABI and it’s a purely software convention. It’s possible a program could use a different convention. FYI, the EBI is defined here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
- If you were to start your coding journey from zero, what would be your plan?
- Need reaources to learn Assembly
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Support for Extension and CSR detection in ELF and linker/loader?
It looks like people are starting to think somewhat along that direction in https://github.com/riscv-non-isa/riscv-elf-psabi-doc etc. but most CPUs that I can think of have basically a monolithic ISA with pretty much an expanding set of instructions as the versions increment and encoded in the -march argument to the linker.
lz4_rv32i_decode
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Need reaources to learn Assembly
Here is a comparably short and readable example for RV32I assembly: https://github.com/enthusi/lz4_rv32i_decode
What are some alternatives?
riscv-isa-manual - RISC-V Instruction Set Manual
jupiter - RISC-V Assembler and Runtime Simulator
open-source-cs - Video discussing this curriculum:
rvalp - RISC-V Assembly Language Programming
curriculum - The open curriculum for learning web development
first_nes - Create your own games for the Nintendo Entertainment System! This "starter" game is easily extensible for your own projects. Includes references.
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!
riscv-hello-asm - Bare metal RISC-V assembly hello world
riscv-asm-manual - RISC-V Assembly Programmer's Manual
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
picocli - Picocli is a modern framework for building powerful, user-friendly, GraalVM-enabled command line apps with ease. It supports colors, autocompletion, subcommands, and more. In 1 source file so apps can include as source & avoid adding a dependency. Written in Java, usable from Groovy, Kotlin, Scala, etc.
rv51 - A RISC-V emulator for the 8051 (MCS-51) microcontroller.