riscv-elf-psabi-doc VS lz4_rv32i_decode

Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...

It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields.

It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks

This one has more info on the ELF output, notably things like how things like relocations and special symbols like %pcrel_hi work: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc

This is a bit dense but that's what I referred to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc. I'm not sure if there's a RISC-V specific assembly tutorial that talks about calling conventions.

The stack is defined by the ABI and it’s a purely software convention. It’s possible a program could use a different convention. FYI, the EBI is defined here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc

It looks like people are starting to think somewhat along that direction in https://github.com/riscv-non-isa/riscv-elf-psabi-doc etc. but most CPUs that I can think of have basically a monolithic ISA with pretty much an expanding set of instructions as the versions increment and encoded in the -march argument to the linker.