renode
gem5
renode | gem5 | |
---|---|---|
3 | 3 | |
1,432 | 1,424 | |
3.7% | 3.9% | |
9.9 | 9.8 | |
2 days ago | 7 days ago | |
RobotFramework | C++ | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
renode
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Emulating IoT Firmware Made Easy: Start Hacking Without the Physical Device
qemu is fine if the IoT device only runs Linux; may want to look into something like https://renode.io/ for a more comprehensive approach.
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Looking for Open Source Emulators or Simulators for Embedded Systems Development on Ubuntu OS
If you're open to using Zephyr RTOS for your project, I've heard Renode is a fantastic option. https://renode.io/
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Do Necessary Tools Exist For RISC-V Verification?
Renode https://github.com/renode/renode
gem5
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Hot Chips 2023: Arm’s Neoverse V2
The idea is to write a C++ model that that produces cycle accurate outputs of the branch predictor, core pipeline, queues, memory latency, cache hierarchy, prefetch behaviour, etc. Transistor level accuracy isn't needed as long as the resulting cycle timings are identical or near identical. The improvement in workload runtime compared to a Verilog simulation is precisely because they aren't trying to model every transistor, but just the important parameters which effect performance.
Let's take a simple example: Instead of modeling a 64-bit adder in all its gory transistor level detail, you can just have the model return the correct data after 1 "cycle" or whatever your ALU latency is. As long as that cycle latency is the same as the real hardware, you'll get an accurate performance number.
What's particularly useful about these models is they enable much easier and faster state space exploration to see how a circuit would perform, well before going ahead with the Verilog implementation, which relatively speaking can take circuit designers ages. "How much faster would my CPU be if it had a 20% larger register file" can be answered in a day or two before getting a circuit designer to go try and implement such a thing.
If you want an open source example, take a look at the gem5 project (https://www.gem5.org). It's not quite as sophisticated as the proprietary models used in industry, but it's a used widely in academia and open source hardware design and is a great place to start.
- Custom Instructions: How do I go from MATCH/MASK to opcode?
What are some alternatives?
riscv-dv - Random instruction generator for RISC-V processor verification
riscv-none-elf-gcc-xpack - A binary xPack with the GNU RISC-V Embedded GCC toolchain with support of WCH RISCV CH56x... "WCH-Interrupt-fast"
PlatformIO - Your Gateway to Embedded Software Development Excellence :alien:
l4re-core - The core components of the L4Re operating system.
riscv-formal - RISC-V Formal Verification Framework
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
sby - SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
CHRONO - High-performance C++ library for multiphysics and multibody dynamics simulations
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
riscv-perf-model - Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
tock - A secure embedded operating system for microcontrollers