pylectronics
netlistsvg
| pylectronics | netlistsvg | |
|---|---|---|
| 1 | 4 | |
| 45 | 589 | |
| - | - | |
| 0.0 | 3.1 | |
| 2 months ago | 4 months ago | |
| Python | JavaScript | |
| MIT License | MIT License |
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pylectronics
netlistsvg
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Generation of "high level" block diagram based on verilog files
Maybe this: https://github.com/nturley/netlistsvg
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Logic Primitive Transformations with Yosys Techmap
Great article. Especially needed since Yosys is very difficult to use.
One tip, maybe. Yosys's Graphviz output is frankly incomprehensible shit, and Graphviz isn't very good at laying out these sorts of graphs. But it also can output the information to JSON with the write_json command which lets you use other better tools, e.g. https://github.com/nturley/netlistsvg
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FPGA Interchange format to enable interoperable FPGA tooling
Soon: there are 15 different formats for passing netlists around.
I have very little hope that any netlist format that comes from Yosys. Not only has it changed a couple times in the last years, but the latest iteration is some JSON-based monstrosity that has to be by far the most inconvenient netlist format ever created (see https://github.com/nturley/netlistsvg/blob/master/test/digit... ) .
- Show HN: Pylectronics – Reproduce digital electronics in Python
What are some alternatives?
myhdl - The MyHDL development repository
beautiful-react-diagrams - 💎 A collection of lightweight React components and hooks to build diagrams with ease 💎
python-fpga-interchange - Python interface to FPGA interchange format
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
chisel - Chisel: A Modern Hardware Design Language
firrtl - Flexible Intermediate Representation for RTL
ideas - Random ideas and interesting ideas for things we hope to eventually do.
cloudmapper - CloudMapper helps you analyze your Amazon Web Services (AWS) environments.