picoMIPS
picoMIPS processor doing affine transformation (by karthik-0398)
riscv_verilator_model
RISCV model for Verilator/FPGA targets (by aignacio)
| picoMIPS | riscv_verilator_model | |
|---|---|---|
| 1 | 2 | |
| 3 | 40 | |
| - | - | |
| 0.0 | 0.0 | |
| over 3 years ago | over 4 years ago | |
| SystemVerilog | C | |
| MIT License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
picoMIPS
Posts with mentions or reviews of picoMIPS.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-03-22.
riscv_verilator_model
Posts with mentions or reviews of riscv_verilator_model.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-29.
-
RISCV sim through Verilator
So far I have found only this repo : https://github.com/aignacio/riscv_verilator_model.git (does not work for me yet)
-
Need help in CPU design
https://github.com/aignacio/riscv_verilator_model Good start...
What are some alternatives?
When comparing picoMIPS and riscv_verilator_model you can also consider the following projects:
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
serv - SERV - The SErial RISC-V CPU
riscv-simple-sv - A simple RISC V core for teaching
gdb-stub - gdb-proxy implementation for bonfire