openwifi VS litedram

There is some open source firmware for very old WiFi chips:

https://wiki.debian.org/Firmware/Open#Radio

There is also some FPGA based open source WiFi chip things:

https://github.com/open-sdr/openwifi

https://news.ycombinator.com/item?id=27133079 :

https://ans.unibs.it/projects/csi-murder/ enabled by https://github.com/open-sdr/openwifi Both partially funded by EU's Horizon2020 program.

Openwifi talk at FOSDEM 2020 https://www.youtube.com/watch?v=8q5nHUWP43U

one of the developments out of his openwifi project is a 'Openwifi CSI fuzzer WiSec21 demo interview' https://www.youtube.com/watch?v=Jp2ImjCnlkQ

https://github.com/open-sdr/openwifi/blob/master/doc/app_not...

You could try the Xilinx ZC706 with an ADI9361 based FMCOMMS board. The OpenWIFI team has a few configurations listed on their readme that are popular: https://github.com/open-sdr/openwifi. I think these setups will still cost >$1000USD and require considerable effort to get going - I don’t know of a <$1000 SDR setup for 5G development that would be easy to setup and get going with. Curious if anyone knows of one.

Nice one Nuand, the BladeRF v2 looks like a very interesting alternative SDR modem to the cheaper Adalm Pluto educational kit by Analog Devices, the manufacturer of the transceiver chip being used by the BladeRF v2.

There is another alternative open source WiFi stack, openwifi and it has been discussed in HN before [2][3].

[1]https://www.analog.com/en/design-center/evaluation-hardware-...

[2 ]https://github.com/open-sdr/openwifi

[3]https://news.ycombinator.com/item?id=24273919

I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.

Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.

You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.

So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.