learn-fpga
flexible-vectors
learn-fpga | flexible-vectors | |
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22 | 4 | |
2,337 | 43 | |
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7.3 | 2.8 | |
19 days ago | 26 days ago | |
C++ | WebAssembly | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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learn-fpga
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FPGA Dev Boards for $150 or Less
I've followed this tutorial recently, and it's amazing:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
The author includes detailed instruction for how to build a micro-controller in Verilog on an icestick, starting from a very simple blinker all the way to a functional RISC-V core.
My other suggestion would be: for most of the toolchain, skip your package manager and directly install the binary artifacts published on this Github repo:
https://github.com/YosysHQ/oss-cad-suite-build
You'll spare yourself a world of pain.
- Top Ten Fallacies About RISC-V (David Patterson)
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What are the best learning resources for a beginner?
You might want to look at https://github.com/BrunoLevy/learn-fpga
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First FPGA Board
Lattice Icestick is pretty cheap and has just enough LUTs to run a small riscv. Also check out https://github.com/BrunoLevy/learn-fpga
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My first Risc-V core in FPGA
Thanks Bruno Levy
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How to Emulate a CPU on an FPGA
These are good starting points: https://github.com/BrunoLevy/learn-fpga/ and, from there, https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md.
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PicoBlaze in Verilog / Vivado
The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
- looking for ideas for a small project using digilent pmod on xilinx zynq 7 series fpga using hdl (verilog).
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Embedded Systems Weekly #125
Rust blinky on RISC-V soft core If you were looking for, an introduction example of an embedded Rust program, running on a RISC-V soft core, check out this blinky that is using the FemtoRV .
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Minimax: A Compressed-First, Microcoded RISC-V CPU
Nope - that's all there is.
It's possible to be incredibly expressive in Verilog and VHDL. This implementation is written in VHDL, which has an outdated reputation for being long-winded.
Also worth a look: FemtoRV32 Quark [0], which is written in Verilog.
[0]: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
flexible-vectors
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Mojo – a new programming language for all AI developers
Wonderful language. Only complaint (so far) : SIMD should be named Vector and dispatched to whatever SIMD/vector pipeline the host offers, similar to Flexible Vectors proposal in WASM: https://github.com/WebAssembly/flexible-vectors/blob/main/pr...
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AVX 512 will be the future
Abstract vectorization instructions in wasm will make life a lot easier
https://github.com/WebAssembly/flexible-vectors/blob/main/pr... great proposal!
Mapping to whatever hardware is available as some sort of micro library
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Take More Screenshots
I think SIMD was a distraction to our conversation, most code doesn't use it and in the future the length agnostic, flexible vectors; https://github.com/WebAssembly/flexible-vectors/blob/master/... are a better solution. They are a lot like RVV; https://github.com/riscv/riscv-v-spec, research around vector processing is why RISC-V exists in the first place!
I was trying to find the smallest Rust Wasm interpreters I could find, I should have read the source first, I only really use wasmtime, but this one looks very interesting, zero deps, zero unsafe.
16.5kloc of Rust https://github.com/rhysd/wain
The most complete wasm env for small devices is wasm3
20kloc of C https://github.com/wasm3/wasm3
I get what you are saying as to be so small that there isn't a place of bugs to hide.
> “There are two ways of constructing a software design: One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies. The first method is far more difficult.” CAR Hoare
Even a 100 line program can't be guaranteed to be free of bugs. These programs need embedded tests to ensure that the layer below them is functioning as intended. They cannot and should not run open loop. Speaking of 300+ reimplementations, I am sure that RISC-V has already exceeded that. The smallest readable implementation is like 200 lines of code; https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
I don't think Wasm suffers from the base extension issue you bring up. It will get larger, but 1.0 has the right algebraic properties to be useful forever. Wasm does require an environment, for archival purposes that environment should be written in Wasm, with api for instantiating more envs passed into the first env. There are two solutions to the Wasm generating and calling Wasm problem. First would be a trampoline, where one returns Wasm from the first Wasm program which is then re-instantiated by the outer env. The other would be to pass in the api to create new Wasm envs over existing memory buffers.
See, https://copy.sh/v86/
MS-DOS, NES or C64 are useful for archival purposes because they are dead, frozen in time along with a large corpus of software. But there is a ton of complexity in implementing those systems with enough fidelity to run software.
Lua, Typed Assembly; https://en.wikipedia.org/wiki/Typed_assembly_language and Sector Lisp; https://github.com/jart/sectorlisp seem to have the right minimalism and compactness for archival purposes. Maybe it is sectorlisp+rv32+wasm.
If there are directions you would like Wasm to go, I really recommend attending the Wasm CG meetings.
https://github.com/WebAssembly/meetings
When it comes to an archival system, I'd like it to be able to run anything from an era, not just specially crafted binaries. I think Wasm meets that goal.
https://gist.github.com/dabeaz/7d8838b54dba5006c58a40fc28da9...
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Exploring SIMD performance improvements in WebAssembly
Thanks! Good points, I think in general the fixed-width "packed" SIMD ISAs have the downsides that you mentioned.
But it seems that WebAssembly doesn't have length-agnostic SIMD instructions yet. There is an open proposal to add this though: https://github.com/WebAssembly/flexible-vectors
What are some alternatives?
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
wain - WebAssembly implementation from scratch in Safe Rust with zero dependencies
bubbleos
rust-wasm - A simple and spec-compliant WebAssembly interpreter
wai - a wasm interpreter written by rust
openfpga - Open FPGA tools
tropy - Research photo management
WasmCert-Isabelle - A mechanisation of Wasm in Isabelle.
Lifeslice - Automatically take webcam pics, screenshot, and other metrics throughout the day.
simd-wasm-profiling - Exploring SIMD performance improvements in WebAssembly