j-core-ice40
icestorm
| j-core-ice40 | icestorm | |
|---|---|---|
| 1 | 7 | |
| 17 | 948 | |
| - | 0.7% | |
| 0.0 | 0.0 | |
| over 4 years ago | 13 days ago | |
| VHDL | Python | |
| - | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
j-core-ice40
-
J2 open processor: an open source processor using the SuperH ISA
I think https://github.com/j-core/j-core-ice40 is the better repo to check out.
icestorm
-
Framework Laptop feature requests – RISC-V Mainboard
I'd also vote for an FPGA Mainboard, ideally Lattice, ideally iCE40, and ideally compatible with Project IceStorm (Yosys, Arachne-pnr, and IceStorm) open source tools:
https://github.com/YosysHQ/icestorm
Think something similar to MiSTer FPGA -- but in a laptop form factor, and able to run all sorts of "soft" CPUs, i.e.:
https://opencores.org/projects?expanded=Processor
- Are there any resources detailing how synthesis happens for a particular FPGA?
- Building the SAP-2 on an FPGA
-
Learning Verilog and FPGA
As others have already mentioned the Lattice ice40 family is supported by OSS chains through project icestorm [0].
There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:
- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/
- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...
[0] https://github.com/YosysHQ/icestorm
-
Thoughts on OSFPGA?
You know the best part about Lattice FPGAs? The iCE40 bitstream has been reverse-engineered. As a result, you can delete Diamond and use a completely open-source toolchain instead. It's so much cleaner, easier, and less bloated that it just shows how awful all the vendor tools have gotten.
- Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
-
J2 open processor: an open source processor using the SuperH ISA
>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.
>Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot.
Nice!
But, it would be an additional serious "would be nice" -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain:
https://www.latticesemi.com/Products
http://www.clifford.at/icestorm/
https://github.com/YosysHQ/icestorm
What are some alternatives?
jcore-j1-ghdl - A simple design targeting iCE40 up5k with GHDL + Yosys.
ghdl-yosys-plugin - VHDL synthesis (based on ghdl)
apio - :seedling: Open source ecosystem for open FPGA boards
prince - The Prince lightweight block cipher in Verilog.
dbus_ti_link_uart_verilog - Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89.
abc - ABC: System for Sequential Logic Synthesis and Formal Verification
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
vhdl-tutorial
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
chisel - Chisel: A Modern Hardware Design Language
6502-exp - 6502 Computer FPGA Peripherals