iob-soc-opencryptolinux VS vivado-risc-v

Compare iob-soc-opencryptolinux vs vivado-risc-v and see what are their differences.

iob-soc-opencryptolinux

Running Linux on IOb-SoC-OpenCryptoHW (by IObundle)
Suggest topics
Source Code
Suggest alternative
Edit details

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro (by eugene-tarassov)
nexys-video risc-v Linux Xilinx vivado Fpga vc707 genesys2 Boom rocketchip kc705 arty-a7 Riscv
Source Code
Suggest alternative
Edit details
InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured
iob-soc-opencryptolinux vivado-risc-v
3 6
9 738
- -
9.4 7.5
9 days ago 4 days ago
C Tcl
MIT License -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

iob-soc-opencryptolinux

Posts with mentions or reviews of iob-soc-opencryptolinux. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-18.

vivado-risc-v

Posts with mentions or reviews of vivado-risc-v. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.
  • Recommendations for RISC-V on FPGA
    7 projects | /r/FPGA | 8 Mar 2023
    Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
  • How can I learn about RISC-V and use case? I want to do a project for begginers
    2 projects | /r/FPGA | 5 Feb 2023
  • Open-source RISC-V CPU projects for contribution
    8 projects | /r/RISCV | 28 Jan 2023
    For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v
  • can one run one a linux distro like debian on an fpga?
    1 project | /r/FPGA | 9 Nov 2022
    I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?
  • Error when preparing a USB for use with an FPGA
    1 project | /r/Ubuntu | 22 Mar 2022
  • Running Hello World on a bare-metal RISC-V FPGA
    3 projects | /r/RISCV | 10 Jan 2022
    But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.

What are some alternatives?

When comparing iob-soc-opencryptolinux and vivado-risc-v you can also consider the following projects:

iob-soc - RISC-V System on Chip Template

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

rocket-chip - Rocket Chip Generator

iob-linux

Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL

neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.

riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine

iob-soc-opencryptolinux vs iob-soc vivado-risc-v vs chipyard iob-soc-opencryptolinux vs cva6 vivado-risc-v vs picorv32 iob-soc-opencryptolinux vs meta-riscv vivado-risc-v vs rocket-chip iob-soc-opencryptolinux vs iob-linux vivado-risc-v vs Rudi-RV32I iob-soc-opencryptolinux vs rocket-chip vivado-risc-v vs neorv32-setups vivado-risc-v vs mempool vivado-risc-v vs riscv-boom