icestorm
prince
| icestorm | prince | |
|---|---|---|
| 7 | 1 | |
| 952 | 7 | |
| 1.2% | - | |
| 0.0 | 3.5 | |
| 24 days ago | 4 months ago | |
| Python | Verilog | |
| ISC License | BSD 2-clause "Simplified" License |
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icestorm
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Framework Laptop feature requests – RISC-V Mainboard
I'd also vote for an FPGA Mainboard, ideally Lattice, ideally iCE40, and ideally compatible with Project IceStorm (Yosys, Arachne-pnr, and IceStorm) open source tools:
https://github.com/YosysHQ/icestorm
Think something similar to MiSTer FPGA -- but in a laptop form factor, and able to run all sorts of "soft" CPUs, i.e.:
https://opencores.org/projects?expanded=Processor
- Are there any resources detailing how synthesis happens for a particular FPGA?
- Building the SAP-2 on an FPGA
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Learning Verilog and FPGA
As others have already mentioned the Lattice ice40 family is supported by OSS chains through project icestorm [0].
There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:
- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/
- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...
[0] https://github.com/YosysHQ/icestorm
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Thoughts on OSFPGA?
You know the best part about Lattice FPGAs? The iCE40 bitstream has been reverse-engineered. As a result, you can delete Diamond and use a completely open-source toolchain instead. It's so much cleaner, easier, and less bloated that it just shows how awful all the vendor tools have gotten.
- Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
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J2 open processor: an open source processor using the SuperH ISA
>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.
>Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot.
Nice!
But, it would be an additional serious "would be nice" -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain:
https://www.latticesemi.com/Products
http://www.clifford.at/icestorm/
https://github.com/YosysHQ/icestorm
prince
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Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
What are some alternatives?
ghdl-yosys-plugin - VHDL synthesis (based on ghdl)
apio - :seedling: Open source ecosystem for open FPGA boards
6502-exp - 6502 Computer FPGA Peripherals
dbus_ti_link_uart_verilog - Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89.
vhdl-tutorial
abc - ABC: System for Sequential Logic Synthesis and Formal Verification
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
jcore-j1-ghdl - A simple design targeting iCE40 up5k with GHDL + Yosys.