hdl VS psram-tang-nano-9k

Have you thought about using ADs source code and pulling what you need to create a front end to their device?

The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl

There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl

I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library

See my reply here: https://github.com/zf3/psram-tang-nano-9k/issues/6

I added a note about his to the controller's readme. "Quick discussion about going above 83Mhz".

Another difference that I find in that W955D8MBYA data sheet compared to W955N8MBY, is that W955D8MBYA does not mention anywhere that differential signaling would be optional: but instead it marks it as required. If that is the case, then the question for Best Behavior(tm) of how to properly feed it LVDS does rise again. ( https://github.com/zf3/psram-tang-nano-9k/issues/1 )