hdl
adi_adrv9371_zc706
| hdl | adi_adrv9371_zc706 | |
|---|---|---|
| 5 | 2 | |
| 1,383 | 8 | |
| 2.3% | - | |
| 9.1 | 10.0 | |
| 3 days ago | over 1 year ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
adi_adrv9371_zc706
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Documentation Update
Time to update the documentation at https://github.com/phase4ground/adi_adrv9371_zc706/blob/adrv9371-zc706-dvbs2-integ/design_docs/cobs_decoder/COBS_dec-Entity-Design.md!
- Design Documentation for an Open Source COBS Decoder in VHDL
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