wit
lion
| wit | lion | |
|---|---|---|
| 5 | 10 | |
| 957 | 242 | |
| 1.1% | 0.0% | |
| 5.3 | 4.5 | |
| 6 months ago | 11 days ago | |
| Haskell | ||
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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wit
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[R] Cross-lingual Wikipedia dataset
There's the Wikipedia Image Text dataset, which has many languages (including English and simple English) aswell as a TF datasets wrapper. https://github.com/google-research-datasets/wit
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[R] Google AI Introduces ‘WIT’, A Wikipedia-Based Image Text Dataset For Multimodal Multilingual Machine Learning
Code for https://arxiv.org/abs/2103.01913 found: https://github.com/google-research-datasets/wit
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Google AI Introduces ‘WIT’, A Wikipedia-Based Image Text Dataset For Multimodal Multilingual Machine Learning
To overcome these limitations, Google research team created a high-quality, large-sized, multilingual dataset called the Wikipedia-Based Image Text (WIT) Dataset. It is created by extracting multiple text selections associated with an image from Wikipedia articles and Wikimedia image links.
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Hacker News top posts: Mar 4, 2021
Wit: Wikipedia-Based Image Text Dataset\ (0 comments)
- Wit: Wikipedia-Based Image Text Dataset
lion
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A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
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C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
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Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
- Lion is a formally verified, 5-stage pipeline RISC-V core
- Lion: A formally verified, 5-stage pipeline RISC-V core
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Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
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Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
What are some alternatives?
witokit - A Python toolkit to generate a tokenized dump of Wikipedia for NLP
prometheus-cpp - Prometheus Client Library for Modern C++
WhereIsAI - AI company, product, and tool collection.
riscv-formal - RISC-V Formal Verification Framework
courses - This repository is a curated collection of links to various courses and resources about Artificial Intelligence (AI)
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cbonsai
atomic-story - Understanding how atomics and memory ordering work
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
libcxx - Project moved to: https://github.com/llvm/llvm-project
VELDT-getting-started - Where Lions Roam: Haskell & Hardware on VELDT
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler