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| ghdl | TDP-11 | |
|---|---|---|
| 26 | 3 | |
| 2,210 | 0 | |
| 2.9% | - | |
| 9.8 | 0.0 | |
| 9 days ago | over 1 year ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 only | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ghdl
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GHDL on mac m1
I downloaded https://github.com/ghdl/ghdl/releases/download/v3.0.0/ghdl-macos-11-mcode.tgz and extracted it to home directory ~.
- How to compile ghdl
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Is the VHDL standard library not publicly available?
The body is here.
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Help on trying to find a FOSS solution to replace Quartus in my class.
GHDL + gtkwave
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If someone is good at programming languages like C, will they be good at description languages like VHDL?
Also, VHDL has its roots in Ada, not Pascal. (In fact, the ghdl simulation tool is written in Ada.)
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What is the netlist file format?
If the goal is simulation, the output of the process is something that can be processed by a standard compiler (like gcc or llvm) or executed by a pseudocode interpreter. See, for example, what is done by ghdl.
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Converting VHDL to Verilog using GHDL
Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues
Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.
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Trouble with GHDL and GCC
Find something newer here.
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ghdl, how to include math_real?
replying to myself: I just installed this nightly on a Win10 box and it seems to "work" based on minimal tests. Note that you need to install MinGW.
TDP-11
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Questions on timing
If you want to take a look at the code, you can have a look at it in the repo.
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Initialize array of std_logic_vector with binary file
The whole file can be found here.
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Create a common bus between multiple components in VHDL
I have all the single components written out in VHDL. You can find the code here: https://github.com/tommasopeduzzi/TDP-11/tree/master/fpga/hdl. I would really appreciate it if someone could take a look and give me some criticism, as this is the first time I write any type of HDL.
What are some alternatives?
logisim-evolution - Digital logic design tool and simulator
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
rust_hdl
hVHDL_fpga_interconnect - interconnecting bus written in VHDL for accessing data in FPGA modules
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
awesome-ada - A curated list of awesome resources related to the Ada and SPARK programming language
gtkwave - GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
VHDL-Guide - VHDL Guide
ASFML - Ada binding to the SFML library
Free-Range-VHDL-book - Latex source files of the open-source book FREE RANGE VHDL
Digital - A digital logic designer and circuit simulator.
go-hdl - Hdl is a tool for easing the work with hardware description languages.