TDP-11
By tommasopeduzzi
hVHDL_fpga_interconnect
interconnecting bus written in VHDL for accessing data in FPGA modules (by hVHDL)
TDP-11 | hVHDL_fpga_interconnect | |
---|---|---|
3 | 3 | |
0 | 5 | |
- | - | |
0.0 | 3.5 | |
over 1 year ago | 11 months ago | |
VHDL | VHDL | |
- | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
TDP-11
Posts with mentions or reviews of TDP-11.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-07-22.
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Questions on timing
If you want to take a look at the code, you can have a look at it in the repo.
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Initialize array of std_logic_vector with binary file
The whole file can be found here.
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Create a common bus between multiple components in VHDL
I have all the single components written out in VHDL. You can find the code here: https://github.com/tommasopeduzzi/TDP-11/tree/master/fpga/hdl. I would really appreciate it if someone could take a look and give me some criticism, as this is the first time I write any type of HDL.
hVHDL_fpga_interconnect
Posts with mentions or reviews of hVHDL_fpga_interconnect.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-07-19.
What are some alternatives?
When comparing TDP-11 and hVHDL_fpga_interconnect you can also consider the following projects:
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
ghdl - VHDL 2008/93/87 simulator