fpga-experiments
By fnoeding
risc-v_pipelined_cpu
RISC-V CPU with a 5-stage pipeline, written in SystemVerilog (by MatejKafka)
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| fpga-experiments | risc-v_pipelined_cpu | |
|---|---|---|
| 1 | 1 | |
| 7 | 0 | |
| - | - | |
| 10.0 | 10.0 | |
| over 1 year ago | about 1 year ago | |
| Python | SystemVerilog | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fpga-experiments
Posts with mentions or reviews of fpga-experiments.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-26.
-
How a CPU works: Bare metal C on my RISC-V toy CPU
You are right :)
Here's the repo: https://github.com/fnoeding/fpga-experiments
I'll update the post with it too.
risc-v_pipelined_cpu
Posts with mentions or reviews of risc-v_pipelined_cpu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-26.
-
How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
When comparing fpga-experiments and risc-v_pipelined_cpu you can also consider the following projects:
qtrvsim - RISC-V CPU simulator for education purposes
Digital - A digital logic designer and circuit simulator.