esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy (by sld-columbia)
| esp | Vitis-HLS-Introductory-Examples | |
|---|---|---|
| 1 | 4 | |
| 297 | 522 | |
| 2.0% | 6.1% | |
| 7.5 | 6.3 | |
| 24 days ago | 18 days ago | |
| C | C++ | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
esp
Posts with mentions or reviews of esp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-19.
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
Vitis-HLS-Introductory-Examples
Posts with mentions or reviews of Vitis-HLS-Introductory-Examples.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-12.
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Roadblocks to HLS development
Synthesis errors on Windows 10 platform - I had installed 2023.2 versions of Vivado and standalone Vitis HLS tools. I had trouble synthesizing and simulating the HLS examples in Vitis HLS. I think this had something to do with the compiler not able to deal with OpenCV libraries. I had cloned the opencv libraries but struggled to understand the instructions given below (which I guess is meant for a linux machine). Also during its launch, the standalone tool keeps stating that it will get deprecated in the future.
- Vivado editor alternatives
-
Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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What is wrong with the following code in vivado hls?
HLS Tiny Tutorials
What are some alternatives?
When comparing esp and Vitis-HLS-Introductory-Examples you can also consider the following projects:
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Vitis-Tutorials - Vitis In-Depth Tutorials
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
litex - Build your hardware, easily!
mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.