dace
DaCe - Data Centric Parallel Programming (by spcl)
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. (by JulianKemmerer)
dace | PipelineC | |
---|---|---|
3 | 46 | |
467 | 544 | |
2.1% | - | |
9.5 | 9.5 | |
3 days ago | 2 days ago | |
Python | Python | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
dace
Posts with mentions or reviews of dace.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-20.
- Looking for HLS frameworks to start deploying DL algorithms on FPGAs
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FPGA high-level programming
I had this recommended to me, but have yet to try it out: https://github.com/spcl/dace
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Moving from Python to OpenCL, any advice?
I've had good experience with dace which has a Python frontend but compiles to both Intel OpenCL and Xilinx HLS (along with GPU and multicore CPU backends). It's the easiest way to get into FPGA programming IMO but you don't quite reach the same performance an FPGA expert might get.
PipelineC
Posts with mentions or reviews of PipelineC.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-03.
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software