cva6
openwifi
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cva6 | openwifi | |
---|---|---|
10 | 10 | |
2,085 | 3,558 | |
4.4% | 2.4% | |
9.7 | 7.6 | |
about 16 hours ago | 22 days ago | |
Assembly | C | |
GNU General Public License v3.0 or later | GNU Affero General Public License v3.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cva6
- CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
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Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
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Some data points on Vivado performance on Ryzen and Alder Lake
I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6
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What is Purism's roadmap for open-source hardware/schematics?
When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.
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XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
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How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
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OpenHW Group and Mitacs announce a $22.5M research program for open-source processors
Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.
openwifi
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Hold on there: WPA3 connections fail after 11 hours
There is some open source firmware for very old WiFi chips:
https://wiki.debian.org/Firmware/Open#Radio
There is also some FPGA based open source WiFi chip things:
https://github.com/open-sdr/openwifi
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WiFi: “beamforming” only begins to describe it (2014)
https://news.ycombinator.com/item?id=27133079 :
https://ans.unibs.it/projects/csi-murder/ enabled by https://github.com/open-sdr/openwifi Both partially funded by EU's Horizon2020 program.
Openwifi talk at FOSDEM 2020 https://www.youtube.com/watch?v=8q5nHUWP43U
- Tesla Coil Zenneck Wave TV White Space Wifi Network
- Any way to transmit 802.11(wifi) signals to a receiver
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Can 5G be used as surveillance radar? U.S. military funds Binghamton research
one of the developments out of his openwifi project is a 'Openwifi CSI fuzzer WiSec21 demo interview' https://www.youtube.com/watch?v=Jp2ImjCnlkQ
https://github.com/open-sdr/openwifi/blob/master/doc/app_not...
- Is there an intersection between FPGA and Wireless Comms?
- How many more years until we have a completely open source RISC-V SOC?
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Ask HN: How to get started with 5G as a software developer
You could try the Xilinx ZC706 with an ADI9361 based FMCOMMS board. The OpenWIFI team has a few configurations listed on their readme that are popular: https://github.com/open-sdr/openwifi. I think these setups will still cost >$1000USD and require considerable effort to get going - I don’t know of a <$1000 SDR setup for 5G development that would be easy to setup and get going with. Curious if anyone knows of one.
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BladeRF-wiphy: open-source IEEE 802.11 compatible Software Defined Radio modem
Nice one Nuand, the BladeRF v2 looks like a very interesting alternative SDR modem to the cheaper Adalm Pluto educational kit by Analog Devices, the manufacturer of the transceiver chip being used by the BladeRF v2.
There is another alternative open source WiFi stack, openwifi and it has been discussed in HN before [2][3].
[1]https://www.analog.com/en/design-center/evaluation-hardware-...
[2 ]https://github.com/open-sdr/openwifi
[3]https://news.ycombinator.com/item?id=24273919
What are some alternatives?
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
bladeRF-wiphy - bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
litex - Build your hardware, easily!
esp32-wifi-penetration-tool - Exploring possibilities of ESP32 platform to attack on nearby Wi-Fi networks.
verilator - Verilator open-source SystemVerilog simulator and lint system
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
gr-ieee802-11 - IEEE 802.11 a/g/p Transceiver
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
direwolf - Dire Wolf is a software "soundcard" AX.25 packet modem/TNC and APRS encoder/decoder. It can be used stand-alone to observe APRS traffic, as a tracker, digipeater, APRStt gateway, or Internet Gateway (IGate). For more information, look at the bottom 1/4 of this page and in https://github.com/wb2osz/direwolf/blob/dev/doc/README.md
litedram - Small footprint and configurable DRAM core
ZynqMP-FPGA-Linux - FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)