coc-pylsp
svls
| coc-pylsp | svls | |
|---|---|---|
| 1 | 3 | |
| 34 | 418 | |
| - | - | |
| 7.7 | 8.1 | |
| about 2 months ago | 4 days ago | |
| TypeScript | Rust | |
| MIT License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
coc-pylsp
-
How to configure vim like an IDE
Python has several here, pylsp, pyright & a fork of vscode-python
svls
-
How to configure vim like an IDE
svls
-
svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
-
Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
I can attest first-hand to the "headache" that comes from semi company simulation environments. Not only are they horribly outdated (in Perl/Tcl), but they're different at every company you work at. There's no gold standard because the standard that these EDA companies ought to be making doesn't exist.
There needs to be an open initiative between semi companies to create a standard simulation environment -- with compilers, unit-test frameworks, and all sorts of simulation (gate-level, analog/mixed signal, emulation, etc). Hell, just give me a free IDE plugin for SystemVerilog that actually works.
This lack of a standard seems to me like the critical path in hardware design. I'm trying to support projects to fix this like SVLS (A language server for SystemVerilog: https://github.com/dalance/svls) but these are all hard problems to solve. This industry is relatively niche and doesn't seem to have many engineers interested in FOSS.
What are some alternatives?
coc-perl - Enable Perl5 language server on VIM/NeoVIM through coc-nvim.
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
kickstart.nvim - A launch point for your personal nvim configuration
veridian - A SystemVerilog Language Server
ale - Check syntax in Vim/Neovim asynchronously and fix files, with Language Server Protocol (LSP) support
texlab - An implementation of the Language Server Protocol for LaTeX
coc-ccls - CCLS (C/C++) extension for coc.nvim
Verilog.jl - Verilog for Julia
language-server-protocol - Defines a common protocol for language servers.
circt - Circuit IR Compilers and Tools
coc-java - Java extension for coc.nvim
RecursiveFactorization.jl